Project: Dimensionality Reduction of Large Semiconductor Production Test Datasets
Description
NXP Semiconductors enables a smarter, safer, and more sustainable world through innovation. As the world leader in secure connectivity solutions for embedded applications, NXP is pushing boundaries in the automotive, industrial & IoT, mobile, and communication infrastructure markets.
In the NXP manufacturing process, checking whether an IC (Integrated Circuit) complies with its specifications is essential to guarantee the quality of devices shipped to the customer. As a result, at the end of the production line, NXP performs electrical measurements covering the chip's area. Nowadays, with the advancement of Silicon technology, the generated test dataset will contain roughly 20,000 electrical measurements, becoming challenging (nearly impossible) to check all the distributions to detect any abnormalities.
Objective
To address this challenge, we aim to use dimensionality reduction techniques to reduce the number of electrical measurement parameters we have to look at and, if possible, to find any natural clusters after reducing the dimensions of the dataset. This Master's thesis explores the topic of dimensionality reduction in an industrial testing environment and its limitations. The focus will be exploring robust (not outlier-sensitive) techniques to highlight the most important parameters and include the most essential information. Production and qualification data will be available for the interested student to perform the following tasks:
• Explore the different Dimensionality Reduction techniques
• Explore the use of Robust methods
• Apply the different Dimensionality Reduction techniques to electrical measurements
• Apply the different Dimensionality Reduction techniques to the data points and parameters
For more information, please visit our website https://www.nxp.com
Details
- Supervisor
-
Fernando Paulovich
- External location
- NXP Semiconductors
- Interested?
- Get in contact